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FEATURES Four High Performance VCAs in a Single Package 0.02% THD No External Trimming 120 dB Gain Range 0.07 dB Gain Matching (Unity Gain) Class A or AB Operation APPLICATIONS Remote, Automatic, or Computer Volume Controls Automotive Volume/Balance/Faders Audio Mixers Compressor/Limiters/Compandors Noise Reduction Systems Automatic Gain Controls Voltage Controlled Filters Spatial Sound Processors Effects Processors GENERAL DESCRIPTION
Low Cost Quad Voltage Controlled Amplifier SSM2164
FUNCTIONAL BLOCK DIAGRAM
VC
IIN
VCA1
IIOUT
VC
IIN
VCA2
IIOUT
VC
The SSM2164 contains four independent voltage controlled amplifiers (VCAs) in a single package. High performance (100 dB dynamic range, 0.02% THD) is provided at a very low cost-per-VCA, resulting in excellent value for cost sensitive gain control applications. Each VCA offers current input and output for maximum design flexibility, and a ground referenced -33 mV/dB control port. All channels are closely matched to within 0.07 dB at unity gain, and 0.24 dB at 40 dB of attenuation. A 120 dB gain range is possible. A single resistor tailors operation between full Class A and AB modes. The pinout allows upgrading of SSM2024 designs with minimal additional circuitry. The SSM2164 will operate over a wide supply voltage range of 4 V to 18 V. Available in 16-pin P-DIP and SOIC packages, the device is guaranteed for operation over the extended industrial temperature range of -40C to +85C.
IIN
VCA3
IIOUT
VC
IIN
VCA4
IIOUT
POWER SUPPLY AND BIASING CIRCUITRY
V+
GND
V-
MODE
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
SSM2164-SPECIFICATIONS
ELECTRICAL SPECIFICATIONS (V = 15 V, A = 0 dB, 0 dBu = 0.775 V rms, V
Parameter AUDIO SIGNAL PATH Noise Headroom Total Harmonic Distortion Conditions VIN = GND, 20 kHz Bandwidth Clip Point = 1% THD+N 2nd and 3rd Harmonics Only AV = 0 dB, Class A AV = 20 dB, Class A1 AV = 0 dB, Class AB AV = 20 dB, Class AB1 CF = 10 pF CF = 10 pF VIN = 0
S V IN = 0 dBu, RIN = ROUT = 30 k, f = 1 kHz, -40C < TA < +85C using Typical Application Circuit (Class AB), unless otherwise noted. Typical specifications apply at TA = +25C.)
Min
SSM2164 Typ Max -94 22 0.02 0.15 0.16 0.3 -110 500 0.7 10 50 0.1 5 -33 -3300 1.5 0.07 0.24 -100 +20 .1
Units dBu dBu % % % % dB kHz mA/s nA nA V k mV/dB ppm/C mV dB dB dB dB V mA dB
Channel Separation Unity Gain Bandwidth Slew Rate Input Bias Current Output Offset Current Output Compliance CONTROL PORT Input Impedance Gain Constant Gain Constant Temperature Coefficient Control Feedthrough Gain Matching, Channel-to-Channel Maximum Attenuation Maximum Gain POWER SUPPLIES Supply Voltage Range Supply Current Power Supply Rejection Ratio
NOTES 1 -10 dBu input @ 20 dB gain; +10 dBu input @ -20 dB gain. 2 After 60 seconds operation. 3 +25C to +85C. Specifications subject to change without notice.
(Note 2) 0 dB to -40 dB Gain Range3 AV = 0 dB AV = -40 dB
8.5
4 Class AB 60 Hz 6 90
18 8
TYPICAL APPLICATION AND TEST CIRCUIT
VC VC4 100pF
14
IIN 30k VIN4 500 560pF
15
13 IIOUT VCA4
30k 1/2 OP275 VOUT4
POWER SUPPLY AND BIASING CIRCUITRY 9 V- 8 16 GND V+ 1 MODE RB (7.5k CLASS A) (OPEN CLASS AB)
0.1F 0.1F
-15V
+15V
Figure 1. RIN = ROUT = 30 k, CF = 100 pF. Optional RB = 7.5 k, Biases Gain Core to Class A Operation. For Class AB, Omit RB.
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Input, Output, Control Voltages . . . . . . . . . . . . . . . . V- to V+ Output Short Circuit Duration to GND . . . . . . . . . Indefinite Storage Temperature Range . . . . . . . . . . . . -65C to +150C Operating Temperature Range . . . . . . . . . . . . . -40C to +85C Junction Temperature Range . . . . . . . . . . . . -65C to +150C Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300C Package Type 16-Pin Plastic DIP (P Suffix) 16-Pin SOIC (S Suffix) JA* 76 92 JC 33 27 Units C/W C/W
ORDERING GUIDE
Model SSM2164P SSM2164S
Temperature Range -40C to +85C -40C to +85C
Package Description Plastic DIP Narrow SOIC
Package Options N-16 R-16A
PIN CONFIGURATION 16-Lead Epoxy DIP and SOIC
*JA is specified for the worst case conditions; i.e., JA is specified for device in socket for P-DIP packages, JA is specified for device soldered in circuit board for SOIC package.
MODE IIN1 VC1 IOUT1 IOUT2 VC2 IIN2 GND
1 2 3 4 5 6 7 8
16 V+ 15 IIN4 14 VC4
SSM2164
13 IOUT4
TOP VIEW 12 IOUT3 (Not to Scale) 11 VC3 10 IIN3 9 V-
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the SSM2164 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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SSM2164 Typical Performance Characteristics
1.0 CLASS A VS = 15V LPF = 80kHz
THD + N - %
AV = + 20dB 0.1 AV = - 20dB
AV = 0dB
0.01 20 100 1k FREQUENCY - Hz 10k 20k
210 200 190 180 170 160 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 0.00 0.05 0.10 0.15 0.20 0.25 THD - %
VS = 15V TA = +25C 1200 CHANNELS
UNITS
0.30
0.35
0.40
0.45
Figure 2. THD+N vs. Frequency, Class A
Figure 5. THD Distribution, Class AB
1.0 CLASS AB VS = 15V LPF = 80kHz AV = +20dB THD + N - % AV = -20dB
1.0 VS 15V AV = 0dB LPF = 22kHz
THD + N - %
0.1
AV = 0dB
CLASS AB 0.1
CLASS A
0.01 20 100 1k FREQUENCY - Hz 10k 20k
0.01 20 100 1k AMPLITUDE - VRMS 10k 20k
Figure 3. THD+N vs. Frequency Class, AB
Figure 6. THD+N vs. Amplitude
300 280 260 240 220 200 VS = 15V TA = +25C 1200 CHANNELS
0.10 LPF = 80kHz 0.08
THD + N - %
180
UNITS
0.06
160 140 120 100 80 60 40 20 0 0.005 0.010
0.04
0.02
0
0.015 0.020 0.025 0.030 THD - % 0.035 0.040 0.045 0.050
0
4
8
12
16
20
SUPPLY - Volts
Figure 4. THD Distribution, Class A
Figure 7. THD+N vs. Supply Voltage, Class A
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1000
0.030
0.025
% THD
VOLTAGE NOISE DENSITY - nV/
VS = 15V VIN = 0dBu AV = 0dB
VS = 15V TA = +25C
Hz
100 10
0.020
0.015
0.010
-40
-20
0 20 40 TEMPERATURE - C
60
80
1k
10k
RBIAS -
100k
1M
Figure 8. THD vs. Temperature, Class A
Figure 11. Voltage Noise Density vs. RBIAS
1.0
0.30
VS = 15V VIN = 0dBu AV = 0dB
VS = 15V TA = +25C
0.25
% THD
0.20
THD - %
-40 -20 0 20 40 TEMPERATURE - C 60 80
0.1
0.15
0.10
0.01 1k 10k RBIAS - 100k 1M
Figure 9. THD vs. Temperature, Class AB
500 VS = 15V RIN = RF = 30k TA = +25C
10
Figure 12. THD vs. RBIAS
CONTROL FEEDTHROUGH - mV
400
5
VS = 15V TA = +25C
Hz
0
300
NOISE - nV/
-5
200
-10
100
-15
0 1 10 100 1k FREQUENCY - Hz 10k 100k
-20 1k 10k RBIAS - 100k 1M
Figure 10. Voltage Noise Density vs. Frequency, Class AB
Figure 13. Control Feedthrough vs. RBIAS
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SSM2164 Typical Performance Characteristics
15 PHASE 10 VS = 15V TA = +25C AV = 0dB CF = 10pF GAIN 0 0 180
-3dB BANDWIDTH - Hz
10M VS = 15V TA = +25C 1M
PHASE - Degrees
5
90
GAIN - dB
-5
-90
100k
-10
-180
-15 1k 10k 100k FREQUENCY - Hz 1M 10M
10k 1 10 100 1000
I TO V FEEDBACK CAPACITOR - pF
Figure 14. Gain/Phase vs. Frequency
0.1 CF = 10pF 0
Figure 17. -3 dB Bandwidth vs. I-to-V Feedback Capacitor
30 SLEW RATE VS = 15V TA = +25C
25
CF = 100pF
GAIN - dB
-0.1 VS = 15V TA = +25C AV = 0dB
SLEW RATE - V/s
20 OP275 OUTPUT AMPLIFIER 15
-0.2
10
-0.3
5
-0.4 10 100 1k FREQUENCY - Hz 10k 100k
0 1 10 I TO V FEEDBACK CAPACITOR - pF 100
Figure 15. Gain Flatness vs. Frequency
Figure 18. Slew Rate vs. I-to-V Feedback Capacitor
40 VS = 15V TA = +25C CF = 10pF
20 VS = 15V TA = +25C VIN = 0V RF = RIN = 30k
AV = 0dB
0
CONTROL FEEDTHROUGH - dB
20
AV = +20dB
0
GAIN - dB
-20
AV = -20dB
-20
-40
-40
-60
-60 100
1k
10k 100k FREQUENCY - Hz
1M
10M
-80 100
1k
10k FREQUENCY - Hz
100k
1M
Figure 16. Bandwidth vs. Gain
Figure 19. Control Feedthrough vs. Frequency
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APPLICATIONS INFORMATION Circuit Description
VS = 15V TA = +25C
-20
PSRR - dB
-40 +PSRR -60 -PSRR -80
The SSM2164 is a quad Voltage Controlled Amplifier (VCA) with 120 dB of gain control range. Each VCA is a current-in, current-out device with a separate -33 mV/dB voltage input control port. The class of operation (either Class A or Class AB) is set by a single external resistor allowing optimization of the distortion versus noise tradeoff for a particular application. The four independent VCAs in a single 16-pin package make the SSM2164 ideal for applications where multiple volume control elements are needed.
V+
-100 10 100 1k 10k FREQUENCY - Hz 100K 1M
Figure 20. PSRR vs. Frequency
IIN
25 VS = 15V TA = +25C
Q5
Q6
Q7
Q8
20
IOUT MODE 4.5k Q1 Q2 Q3 Q4 450 500 VC
SUPPLY CURRENT - mA
+ISY 15
-ISY 10
5
0 1k 10k RBIAS - 100k 1M
V-
Figure 23. Simplified Schematic (One Channel) Figure 21. Supply Current vs. RBIAS
-45 CLASS A AND CLASS AB -40
GAIN CONSTANT - mV/dB
VS = 15V -35
The simplified schematic in Figure 23 shows the basic structure of one of the four VCAs in the device. The gain core is comprised of the matched differential pairs Q1-Q4 and the current mirrors of Q5, Q6 and Q7, Q8. The current input pin, IIN, is connected to the collectors of Q1 and Q7, and the difference in current between these two transistors is equivalent to IIN. For example, if 100 A is flowing into the input, Q1's collector current will be 100 A higher than Q7's collector current. Varying the control voltage VC, steers the signal current from one side of each differential pair to the other, resulting in either gain or attenuation. For example, a positive voltage on VC steers more current through Q1 and Q4 and decreases the current in Q2 and Q3. The current output pin, IOUT, is connected to the collector of Q3 and the current mirror (Q6) from Q2. With less current flowing through these two transistors, less current is available at the output. Thus, a positive VC attenuates the input and a negative VC amplifies the input. The VCA has unity gain for a control voltage of 0.0 V where the signal current is divided equally between the gain core differential pairs. The MODE pin allows the setting of the quiescent current in the gain core of the VCA to trade off the SSM2164's THD and noise performance to an optimal level for a particular application. Higher current through the core results in lower distortion
-30
-25
-20 -50
-25
0
25
50
75
100
TEMPERATURE - C
Figure 22. Gain Constant vs. Temperature
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SSM2164
but higher noise, and the opposite is true for less current. The increased noise is due to higher current noise in the gain core transistors as their operating current is increased. THD has the opposite relationship to collector current. The lower distortion is due to the decrease in the gain core transistors' emitter impedance as their operating current increases. This classical tradeoff between THD and noise in VCAs is usually expressed as the choice of using a VCA in either Class A or Class AB mode. Class AB operation refers to running a VCA with less current in the gain core, resulting in lower noise but higher distortion. More current in the core corresponds to Class A performance with its lower THD but higher noise. Figures 11 and 12 show the THD and noise performance of the SSM2164 as the bias current is adjusted. Notice the two characteristics have an inverse characteristic. The quiescent current in the core is set by adding a single resistor from the positive supply to the MODE pin. As the simplified schematic shows, the potential at the MODE pin is one diode drop above the ground pin. Thus, the formula for the MODE current is: I MODE = (V +) - 0.6V RB a low cutoff frequency. The main exception to this is in dynamic processing applications, where faster attack or decay times may be needed.
+5V 100k 1F 30k VIN1 500 +5V 100k 1F 560pF
VC
3
100pF
IIN
2
VCA1
4
IIOUT
30k 1/4 OP482 VOUT1
VC
6
100pF
IIN 30k VIN2 500 +5V 100k 1F 30k VIN3 500 +5V 100k 1F 30k VIN4 500 560pF IIN 560pF VC IIN 560pF VC
7
VCA2
5
IIOUT
30k 1/4 OP482 VOUT2
11
100pF
10
VCA3
12 IIOUT
30k 1/4 OP482 VOUT3
With 15 V supplies, an RB of 7.5k gives Class A biasing with a current of 1.9 mA. Leaving the MODE pin open sets the SSM2164 in Class AB with 30 A of current in the gain core.
Basic VCA Configuration
14
100pF
15
13 IIOUT VCA4
30k 1/4 OP482 VOUT4
Figure 24 shows the basic application circuit for the SSM2164. Each of the four channels is configured identically. A 30 k resistor converts the input voltage to an input current for the VCA. Additionally, a 500 resistor in series with a 560 pF capacitor must be added from each input to ground to ensure stable operation. The output current pin should be maintained at a virtual ground using an external amplifier. In this case the OP482 quad JFET input amplifier is used. Its high slew rate, wide bandwidth, and low power make it an excellent choice for the current-to-voltage converter stage. A 30 k feedback resistor is chosen to match the input resistor, giving unity gain for a 0.0 V control voltage. The 100 pF capacitors ensure stability and reduce high frequency noise. They can be increased to reduce the low pass cutoff frequency for further noise reduction. For this example, the control voltage is developed using a 100 k potentiometer connected between +5 V and ground. This configuration results in attenuation only. To produce both gain and attenuation, the potentiometer should be connected between a positive and negative voltage. The control input has an impedance of 5 k. Because of this, any resistance in series with VC will attenuate the control signal. If precise control of the gain and attenuation is required, a buffered control voltage should be used. Notice that a capacitor is connected from the control input to ground. Because the control port is connected directly to the gain core transistors, any noise on the VC pin will increase the output noise of the VCA. Filtering the control voltage ensures that a minimal amount of noise is introduced into the VCA, allowing its full performance to be realized. In general, the largest possible capacitor value should be used to set the filter at
POWER SUPPLY AND BIASING CIRCUITRY 9 V- 8 16 GND V+ 1 MODE RB (7.5k CLASS A) (OPEN CLASSAB)
0.1F 0.1F
-15V
+15V
Figure 24. Basic Quad VCA Configuration
Low Cost, Four-Channel Mixer
The four VCAs in a single package can be configured to create a simple four-channel mixer as shown in Figure 25. The inputs and control ports are configured the same as for the basic VCA, but the outputs are summed into a single output amplifier. The OP176 is an excellent amplifier for audio applications because of its low noise and distortion and high output current drive. The amount of signal from each input to the common output can be independently controlled using up to 20 dB of gain or as much as 100 dB of attenuation. Additional SSM2164s could be added to increase the number of mixer channels by simply summing their outputs into the same output amplifier. Another possible configuration is to use a dual amplifier such as the OP275 to create a stereo, two channel mixer with a single SSM2164.
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SSM2164
VC 30k 500 560pF IIOUT IIN VC 30k IIOUT 500 560pF OP176 VC 30k 500 560pF VC 30k IIOUT 500 560pF VCA4 IIN FROM ADDITIONAL SSM2164s FOR > 4 CHANNELS IIOUT IIN VCA3 VOUT IIN VCA2 30k VCA1
100pF
If additional SSM2164s are added, the 100 pF capacitor may need to be increased to ensure stability of the output amplifier. Most op amps are sensitive to capacitance on their inverting inputs. The capacitance forms a pole with the feedback resistor, which reduces the high frequency phase margin. As more SSM2164's are added to the mixer circuit, their output capacitance and the parasitic trace capacitance add, increasing the overall input capacitance. Increasing the feedback capacitor will maintain the stability of the output amplifier.
Digital Control of the SSM2164
POWER SUPPLY AND BIASING CIRCUITRY
V+
GND
V-
MODE
One option for controlling the gain and attenuation of the SSM2164 is to use a voltage output digital-to-analog converter such as the DAC8426 (Figure 26), whose 0 V to +10 V output controls the SSM2164's attenuation from 0 dB to -100 dB. Its simple 8-bit parallel interface can easily be connected to a microcontroller or microprocessor in any digitally controlled system. The voltage output configuration of the DAC8426 provides a low impedance drive to the SSM2164 so the attenuation can be controlled accurately. The 8-bit resolution of the DAC and its full-scale voltage of +10 V gives an output of 3.9 mV/bit. Since the SSM2164 has a -33 mV/dB gain constant, the overall control law is 0.12 dB/bit or approximately 8 bits/dB. The input and output configuration for the SSM2164 is the same as for the basic VCA circuit shown earlier. The 4-to-1 mixer configuration could also be used.
Figure 25. Four-Channel Mixer (4 to 1)
+15V VREFOUT +10V 4 VDD 18
VC
IIN VCA1 VC 2
IIOUT
DAC8426
10V REFERENCE LATCH A DAC A 1 VOUTA
IIN VCA2 VOUTB VC 20 LATCH C DAC C 19 LATCH D WR A1 A0 15 16 17 LOGIC CONTROL DAC D VOUTD VC VOUTC IIN VCA3 7 14 DATA BUS LATCH B DAC B
IIOUT
MSB LSB
IIOUT
IIOUT 3 VSS VCA4 5 AGND 6 DGND POWER SUPPLY AND BIASING CIRCUITRY IIN
V+
GND
V- MODE
+15V
-15V
Figure 26. Digital Control of VCA Gain
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SSM2164
Single Supply Operation Upgrading SSM2024 Sockets
The SSM2164 can easily be operated from a single power supply as low as +8 V or as high as +36 V. The key to using a single supply is to reference all ground connections to a voltage midway between the supply and ground as shown in Figure 27. The OP176 is used to create a pseudo-ground reference for the SSM2164. Both the OP482 and OP176 are single supply amplifiers and can easily operate over the same voltage range as the SSM2164 with little or no change in performance.
V+ = +8V (1.8k FOR CLASS A) RB (OPEN FOR CLASS B) 16 V+ 10F 30k VIN 500 560pF V- 9 V+ VC (0dB GAIN AT VC = V+ ) 2 V+/2 V+ GND 8 1 V+ MODE 1/4 OP482 100pF 30k
The SSM2164 is intended to replace the SSM2024, an earlier generation quad VCA. The improvements in the SSM2164 have resulted in a part that is not a drop-in replacement to the SSM2024, but upgrading applications with the SSM2024 is a simple task. The changes are shown in Figure 28. Both parts have identical pinouts with one small exception. The MODE input (Pin 1) does not exist on the SSM2024. It has fixed internal biasing, whereas flexibility was designed into the SSM2164. A MODE set resistor should be added for Class A operation, but if the SSM2164 is going to be operated in Class AB, no external resistor is needed.
10k VC1 3 16 1 VIN1
VOUT
V+ NC 10k 4 VOUT1
10k
2
SSM2024 8 9 V-
200
OP176
10k
VC1 3
10F
V+
TO ADDITIONAL OP482 AMPLIFIERS
10k
16 1 VIN1 30k 2
RB 30k 4 VOUT1
SSM2164
8 9 V-
500
Figure 27. Single Supply Operation of the SSM2164 (One Channel Shown)
560pF
The reference voltage is set by the resistor divider from the positive supply. Two 10 k resistors create a voltage equal to the positive supply divided by 2. The 10 F capacitor filters the supply voltage, providing a low noise reference to the circuit. This reference voltage is then connected to the GND pin of the SSM2164 and the noninverting inputs of all the output amplifiers. It is important to buffer the resistor divider with the OP176 to ensure a low impedance pseudo-ground connection for the SSM2164. The input can either be referenced to this same mid-supply voltage or ac coupled as is done in this case. If the entire system is single supply, then the input voltage will most likely already be referenced to the midpoint; if this is the case, the 10 F input capacitor can be eliminated. Unity gain is set when VC equals the voltage on the GND pin. Thus, the control voltage should also be referenced to the same midsupply voltage. The value of the MODE setting resistor may also change depending on the total supply voltage. Because the GND pin is at a pseudo-ground potential, the equation to set the MODE current now becomes: I MODE = (V +) -V GND - 0.6V RB
Figure 28. Upgrading SSM2024 Sockets with SSM2164
Since both parts are current output devices, the output configuration is nearly identical, except that the 10 k resistors should be increased to 30 k to operate the SSM2164 in its optimum range. The 10 k input resistor for the SSM2024 should also be increased to 30 k to match the output resistor. Additionally, the 200 resistor should be replaced by a 500 resistor in series with 560 pF for the SSM2164 circuit. One last change is the control port configuration. The SSM2024's control input is actually a current input. Thus, a resistor was needed to change the control voltage to a current. This resistor should be removed for the SSM2164 to provide a direct voltage input. In addition, the SSM2024 has a log/log control relationship in contrast to the SSM2164's linear/log gain constant. The linear input is actually much easier to control, but the difference may necessitate adjusting a SSM2024 based circuit's control voltage gain curve. By making these relatively simple changes, the superior performance of the SSM2164 can easily be realized.
The value of 1.8 k results in Class A biasing for the case of using a +8 V supply.
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SSM2164
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Pin Plastic DIP (N-16)
16 PIN 1 1 0.840 (21.33) 0.745 (18.93) 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.060 (1.52) 0.015 (0.38) 8 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 9 0.280 (7.11) 0.240 (6.10)
0.130 (3.30) MIN SEATING PLANE
0.015 (0.381) 0.008 (0.204)
0.100 (2.54) BSC
16-Pin Narrow SOIC (R-16A)
16
9 0.1574 (4.00) 0.1497 (3.80)
PIN 1 1 8
0.2440 (6.20) 0.2284 (5.80)
0.3937 (10.00) 0.3859 (9.80) 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.0500 (1.27) BSC 0.0192 (0.49) 0.0138 (0.35) 8 0
0.0196 (0.50) x 45 0.0099 (0.25)
0.0099 (0.25) 0.0075 (0.19)
0.0500 (1.27) 0.0160 (0.41)
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C1969-10-10/94
PRINTED IN U.S.A.

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